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VMCS数据结构(二) [复制链接]

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只看楼主 倒序阅读 使用道具 楼主  发表于: 2016-02-02


VMCS数据结构(二)

发表于 2015 年 11 月 15 日

24.6 VM-EXECUTION CONTROL FIELDS
The VM-execution control fields govern(管理) VMX non-root operation. These are described in Section 24.6.1 through Section 24.6.8.
24.6.1 Pin-Based VM-Execution Controls
The pin-based VM-execution controls constitute a 32-bit vector that governs the handling of asynchronous events (for example: interrupts).1 Table 24-5 lists the controls. See Chapter 27 for how these controls affect processor behavior in VMX non-root operation
pin-based VM执行控制构成一个管理异步事件的32位向量(例如:中断),Table 24-5列举了这些控制,详细看Chapter 27: 这些控制是如何影响VMX根模式的处理器行为的
All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs IA32_VMX_PINBASED_CTLS and IA32_VMX_TRUE_PINBASED_CTLS (see Appendix A.3.1) to determine how to set reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail
所有的其他位都是保留位,一些是0,一些是1,软件应该询问MSR寄存器:A32_VMX_PINBASED_CTLS 和 IA32_VMX_TRUE_PINBASED_CTLS 来确定如何设置这些保留位,错误的设置这些保留位会造成VM-ENTRY失败
The first processors to support the virtual-machine extensions supported only the 1-settings of bits 1, 2, and 4. The VMX capability MSR IA32_VMX_PINBASED_CTLS will always report that these bits must be 1. Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR IA32_VMX_TRUE_PINBASED_CTLS MSR, and software should consult this MSR to discover support for the 0-settings of these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.
处理器的虚拟机扩展仅仅bit1 bit2 bit4为1时,才被支持, IA32_VMX_PINBASED_CTLS将总是报道这些位必须是1,支持任何这些位为0的处理器,将支持VMXMSR IA32_VMX_TRUE_PINBASED_CTLS 寄存器,软件应该通过这个MSR寄存器去发现关于这些位为0的支持,软件并不知道任何这些位的功能应该设置某个位为1
24.6.2 Processor-Based VM-Execution Controls
The processor-based VM-execution controls constitute two 32-bit vectors that govern the handling of synchronous events, mainly those caused by the execution of specific instructions. These are the primary processor-based VM-execution controls and the secondary processor-based VM-execution controls. Table 24-6 lists the primary processor-based VM-execution controls. See Chapter 25 for more details of how these
controls affect processor behavior in VMX non-root operation.
processor-based VM执行控制构成了两个向量来管理异步事件的处理,这些事件主要是通过执行特殊的指令产生的(Some instructions cause VM exits regardless(不理会) of the settings of the processor-based VM-execution controls),这两个向量一个是primary processor-based,一个是secondary processor-based,Table 24-6列举了primary processor-based,Chapter 25介绍了更多的细节,非根模式下这些控制是影响处理器行为的
All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs IA32_VMX_PROCBASED_CTLS and IA32_VMX_TRUE_PROCBASED_CTLS (see Appendix A.3.2) to determine how
to set reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section 26.2.1.1).
这个字段的其他位是保留位,一些是0,一些是1,软件应该通过查询 IA32_VMX_PROCBASED_CTLS 和 IA32_VMX_TRUE_PROCBASED_CTLS 去确定如何设置这些保留位,错误的设置这些位会造成VM-ENTRY失败
The first processors to support the virtual-machine extensions supported only the 1-settings of bits 1, 4–6, 8, 13–16, and 26. The VMX capability MSR IA32_VMX_PROCBASED_CTLS will always report that these bits must be 1.Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR IA32_VMX_TRUE_PROCBASED_CTLS MSR, and software should consult this MSR to discover support for the 0-settings of these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.
仅仅当bit 1, 4-6,8,13-16,26为1的时候,处理器的虚拟机扩展才被支持,MSR IA32_VMX_PROCBASED_CTLS将总是报道这些位必须是1,处理器支持设置任何位为0通过 IA32_VMX_TRUE_PROCBASED_CTLS,软件应该通过这个MSR发现哪些位支持为0,不知道任何这些位功能的软件应该设置为1
Bit 31 of the primary processor-based VM-execution controls determines whether the secondary processor-based VM-execution controls are used. If that bit is 0, VM entry and VMX non-root operation function as if all the secondary processor-based VM-execution controls were 0. Processors that support only the 0-setting of bit 31 of the primary processor-based VM-execution controls do not support the secondary processor-based VM-execution controls.
VM执行控制字段的 primary processor-based的Bit 31决定是否使用secondary processor-based, 如果这个位是0,VM-ENTRY和VMX根模式的功能就好像secondary processor-based的控制是0, so, 处理只支持primary processor-based的bit 31设置为0,不支持secondary prcessor-based执行控制
Table 24-7 lists the secondary processor-based VM-execution controls. See Chapter 25 for more details of how these controls affect processor behavior in VMX non-root operation.
表24-7列举了secondary processor-based执行控制字段,Chapter 25介绍了更多关于根模式下,这些控制是如何影响处理器行为的细节                                                                
All other bits in this field are reserved to 0. Software should consult the VMX capability MSR IA32_VMX_PROCBASED_CTLS2 (see Appendix A.3.3) to determine which bits may be set to 1. Failure to clear reserved bits causes subsequent VM entries to fail (see Section 26.2.1.1).
这个字段的其他位被保留为0,软件应该查询 IA32_VMX_PROCBASED_CTLS2来决定哪个位是1,错误的清除保留位会造成VM-ENTRY失败
24.6.3 Exception Bitmap
    The exception bitmap is a 32-bit field that contains one bit for each exception. When an exception occurs, its vector is used to select a bit in this field. If the bit is 1, the exception causes a VM exit. If the bit is 0, the exception is delivered normally through the IDT, using the descriptor corresponding to the exception’s vector.
异常位图是一个32位的字段,每个异常对应一个位,当异常发生的时候,它的向量被用于选择这个字段的一个位,如果这个位是1,异常将会造成一个VM-EXIT,如果这个位是0,异常将被正常的交付给IDT,使用异常的向量对应的描述符
    Whether a page fault (exception with vector 14) causes a VM exit is determined by bit 14 in the exception bitmap as well as the error code produced by the page fault and two 32-bit fields in the VMCS (the page-fault error-code mask and page-fault error-code match). See Section 25.2 for details.
  页错误是否会造成VM-EXIT,不但取决于异常位图的bit 14,而且还与页错误产生的错误码和VMCS中的两个32位字段有关( page-fault error-code mask , page-fault error-code match   )

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