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VMCS数据结构(一) [复制链接]

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VMCS数据结构(一)

发表于 2015 年 11 月 15 日

24.3 ORGANIZATION OF VMCS DATA
The VMCS data are organized into six logical groups:
VMCS数据结构分为六组
• Guest-state area. Processor state is saved into the guest-state area on VM exits and loaded from there on VM entries.
客户机状态区:VM-EXIT的时候,处理器状态被保存到这里,VM-ENTRY的时候,从这里加载客户机状态
• Host-state area. Processor state is loaded from the host-state area on VM exits.
宿主机状态区:VM-EXIT时,处理器状态从这里加载
• VM-execution control fields. These fields control processor behavior in VMX non-root operation. They determine in part the causes of VM exits.
VM执行控制字段,这些字段控制VMX非根模式中处理器的行为,他么确定一部分VM-EXIT的原因
• VM-exit control fields. These fields control VM exits.
• VM-entry control fields. These fields control VM entries.
• VM-exit information fields. These fields receive information on VM exits and describe the cause and the nature of VM exits. On some processors, these fields are read-only.
VM-EXIT信息字段: 这些字段接收VM-EXIT的信息和原因,和VM-EXIT的性质,在一些处理器当中,这些字段是只读的
The VM-execution control fields, the VM-exit control fields, and the VM-entry control fields are sometimes referred to collectively as VMX controls.
VM执行控制字段,VM退出控制字段,VM进入控制字段有时统称为VMX控制
24.4 GUEST-STATE AREA
This section describes fields contained in the guest-state area of the VMCS. As noted earlier, processor state is loaded from these fields on every VM entry (see Section 26.3.2) and stored into these fields on every VM exit (see Section 27.3).
本节描述了VMCS数据结构的guest-stae区域的字段,正如前文提到的,VM-ENTRY的时候,处理器状态从这里加载,VM-EXIT的时候,处理器状态保存到这里
24.4.1 Guest Register State
The following fields in the guest-state area correspond to processor registers:
下面客户机区域的字段对应着处理器的寄存器,32 位处理器不支持英特尔 64 位架构
• Control registers CR0, CR3, and CR4
• Debug register DR7
• RSP, RIP, and RFLAGS
• The following fields for each of the registers CS, SS, DS, ES, FS, GS, LDTR, and TR:
— Selector (16 bits).          16位的选择子
— Base address (64 bits; 32 bits on processors that do not support Intel 64 architecture). The base-address  fields for CS, SS, DS, and ES have only 32 architecturally-defined bits; nevertheless, the corresponding VMCS fields have 64 bits on processors that support Intel 64 architecture.
基址--CS SS DS 和ES 字段仅仅是32位架构的定义,虽然如此,对应的VMCS字段却支持64位体系的处理器
— Segment limit (32 bits). The limit field is always a measure in bytes.
段界限--该字段总是字节尺寸
— Access rights (32 bits). The format of this field is given in Table 24-2 and detailed as follows:
访问属性--该字段的格式显示在了图24-2中,细节如下:
• The low 16 bits correspond to bits 23:8 of the upper 32 bits of a 64-bit segment descriptor. While bits 19:16 of code-segment and data-segment descriptors correspond to the upper 4 bits of the segmen limit, the corresponding bits (bits 11:8) are reserved in this VMCS field.
图中的低16位对应着64位段描述符中的高32位的bit 23:8,当代码段的bit 19:16和数据段描述符对应着段界限上的4bit时,对应的bit 11:8在VMCS字段将被保留
• Bit 16 indicates an unusable segment. Attempts to use such a segment fault except in 64-bit mode. In general, a segment register is unusable if it has been loaded with a null selector.
bit 16标志着一个不可用的段,除了64位模式下,试图使用这个段将会错误,通常,如果段寄存器加载了0,它将是不可用的
• Bits 31:17 are reserved.
The base address, segment limit, and access rights compose the “hidden” part (or “descriptor cache”) of each segment register. These data are included in the VMCS because it is possible for a segment register’s descriptor cache to be inconsistent with the segment descriptor in memory (in the GDT or the LDT) referenced by the segment register’s selector
段基址,界限和属性组成了每个段寄存器的隐藏部分(或者叫描述符区),这些数据之所以在VMCS中,是因为一个段寄存器的描述符区可能与通过段选择子引用的GDT/LDT内存的段描述符不同(客户机保护模式下都有描述符区,如果进入了VT后,修改了选择子,那么再次进入客户机保护模式下,会发生不同,所以VM-EXIT的时候,会先保存描述符区)
The value of the DPL field for SS is always equal to the logical processor’s current privilege level (CPL).
SS的DPL值总是与处理器的CPL相同
• The following fields for each of the registers GDTR and IDTR:
— Base address (64 bits; 32 bits on processors that do not support Intel 64                architecture).            基址
— Limit (32 bits). The limit fields contain 32 bits even though these fields are specified   as only 16 bits in the architecture. GDTT/LDTR的界限是32位,即使字段被指定在16位体系下
• The following MSRs:
— IA32_DEBUGCTL (64 bits)
— IA32_SYSENTER_CS (32 bits)
— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits on processors that do not support Intel 64 architecture)
— IA32_PERF_GLOBAL_CTRL (64 bits). This field is supported only on processors that support the 1-setting of the “load IA32_PERF_GLOBAL_CTRL” VM-entry control.
只有处理器支持的VM-ENTRY控制字段的“load IA32_PERF_GLOBAL_CTRL”为1时,该为才被支持
— IA32_PAT (64 bits). This field is supported only on processors that support either the 1-setting of the “load IA32_PAT” VM-entry control or that of the “save IA32_PAT” VM-exit control.
只有处理器支持的VM-ENTRY控制字段的“load IA32_PAT”或者VM-EXIT字段的"save IA32_PAT"为1时,该为才被支持
— IA32_EFER (64 bits). This field is supported only on processors that support either the 1-setting of the “load IA32_EFER” VM-entry control or that of the “save IA32_EFER” VM-exit control.
只有处理器支持的VM-ENTRY控制字段的“load IA32_EFER” 或者 VM-EXIT控制字段的
“save IA32_EFER”控制字段为1时,该为才被支持
• The register SMBASE (32 bits). This register contains the base address of the logical processor’s SMRAM image.
SMBASE寄存器包含着逻辑处理器SMRAM镜像的基址
24.4.2 Guest Non-Register State
In addition to the register state described in Section 24.4.1, the guest-state area includes the following fields that characterize guest state but which do not correspond to processor registers:
除了24.4.1节描述的寄存器状态,客户机区域还包含了不对应寄存器的具有客户机状态的下列字段
• Activity state (32 bits). This field identifies the logical processor’s activity state. When a logical processor is executing instructions normally, it is in the active state. Execution of certain instructions and the occurrence of certain events may cause a logical processor to transition to an inactive state in which it ceases to execute instructions.
活跃状态:该字段定义了处理器的活跃状态,当处理器正常执行指令的时候,它是active状态,当执行了特点的指令或者发生了特定的时间,处理器也许会变成inactive状态,停止执行指令 (Execution of the MWAIT instruction may put a logical processor into an inactive state.)
The following activity states are defined:
— 0: Active. The logical processor is executing instructions normally.
— 1: HLT. The logical processor is inactive because it executed the HLT instruction.
— 2: Shutdown. The logical processor is inactive because it incurred a triple fault1 or some other serious error.   处理器是inactive,由于它带来了三重错误或者一些严重错误
— 3: Wait-for-SIPI. The logical processor is inactive because it is waiting for a startup-IPI (SIPI).
• Interruptibility state (32 bits). The IA-32 architecture includes features that permit certain events to be blocked for a period of time. This field contains information about such blocking. Details and the format of this field are given in Table 24-3.
可中断状态: 32位体系有一些特征,允许一个特点的事件被阻塞一段时间,这些字段包含了阻塞信息,24-3中介绍了字段的细节和格式

Pending debug exceptions (64 bits; 32 bits on processors that do not support Intel 64 architecture). IA-32 processors may recognize one or more debug exceptions without immediately delivering them. This field contains information about such exceptions. This field is described in Table 24-4.
等待调试异常:32处理器也许会识别一个或多个异常而不会立即交付它们,这个字段包含了异常的信息,24-4中描述了这个字段

• VMCS link pointer (64 bits). If the “VMCS shadowing” VM-execution control is 1, the VMREAD and VMWRITE instructions access the VMCS referenced by this pointer (see Section 24.10). Otherwise, software should set this field to FFFFFFFF_FFFFFFFFH to avoid VM-entry failures (see Section 26.3.1.5).
VMCS link pointer(64位):如果VM执行控制字段的“VMCS shadowing” 字段为1,VMREAD和VMWRITE指令访问VMCS会通过这个pointer,否则,软件应该设置这个字段为FFFFFFFF-FFFFFFFF,避免VM-ENTRY失败
• VMX-preemption timer value (32 bits). This field is supported only on processors that support the 1-setting of the “activate VMX-preemption timer” VM-execution control. This field contains the value that the VMX preemption timer will use following the next VM entry with that setting. See Section 25.5.1 and Section 26.6.4.
VMX 抢占计时器值:只有处理器支持VM执行控制字段的“active VMX-preemption timer”
为1,该字段才被支持,这个字段包含抢占计时器的值将被使用,在下次VM-ENTRY的设置中
• Page-directory-pointer-table entries (PDPTEs; 64 bits each). These four (4) fields (PDPTE0, PDPTE1,PDPTE2, and PDPTE3) are supported only on processors that support the 1-setting of the “enable EPT” VMexecution control. They correspond to the PDPTEs referenced by CR3 when PAE paging is in use (see Section 4.4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). They are used only if the “enable EPT” VM-execution control is 1.
PDPT entry: 只用处理器的VM执行控制字段的“enable EPT”为1的时候,这个字段才被支持,当PAE模式开启的时候,它们对应着通过CR3引用的PDPTE,只用"enable EPT"为1的时候,它们才能被使用
• Guest interrupt status (16 bits). This field is supported only on processors that support the 1-setting of the “virtual-interrupt delivery” VM-execution control. It characterizes part of the guest’s virtual-APIC state and does not correspond to any processor or APIC registers. It comprises two 8-bit subfields:
客户机中断状态:只有VM执行控制字段的“virtual-interrupt delivery”为1的时候,该字段才被支持,它描述的是部分客户机的virtual-apic状态的一部分,并且不对应任何处理器的APIC寄存器,它由两个8位组成
— Requesting virtual interrupt (RVI). This is the low byte of the guest interrupt status. The processor treats this value as the vector of the highest priority virtual interrupt that is requesting service. (The value 0 implies that there is no such interrupt.)
请求虚拟中断:这是客户机中断状态的低8位,处理器把这些值作为请求服务的最高优先级虚拟中断向量。
— Servicing virtual interrupt (SVI). This is the high byte of the guest interrupt status. The processor treats this value as the vector of the highest priority virtual interrupt that is in service. (The value 0 implies that there is no such interrupt.) See Chapter 29 for more information on the use of this field.
服务虚拟中断:这是客户机中断状态的高8位,处理器把这个值作为服务最高优先级虚拟中断向量
24.5 HOST-STATE AREA
This section describes fields contained in the host-state area of the VMCS. As noted earlier, processor state is loaded from these fields on every VM exit (see Section 27.5).
All fields in the host-state area correspond to processor registers:
这节描述了VMCS的宿主机区域,正如前文所述,VM-EXIT的时候,处理器从这些字段中加载状态,宿主机区域的所有字段对应着处理器寄存器,32位处理器不支持64位体系
• CR0, CR3, and CR4
• RSP and RIP
• Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS, and TR. There is no field in the host-state area for the LDTR selector.
宿主机区域没有LDTR选择子
• Base-address fields for FS, GS, TR, GDTR, and IDTR
• The following MSRs:
— IA32_SYSENTER_CS (32 bits)
— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP
— IA32_PERF_GLOBAL_CTRL (64 bits).:
1-setting of the “load IA32_PERF_GLOBAL_CTRL” VM-exit control.
— IA32_PAT (64 bits).:
1-setting of the “loadIA32_PAT” VM-exit control.
— IA32_EFER (64 bits). :
1-setting of the “load IA32_EFER” VM-exit control.
In addition to the state identified here, some processor state components are loaded with fixed values on every VM exit; there are no fields corresponding to these components in the host-state area.
除了这里定义的状态外,部分处理器的状态会从固定值加载,宿主机区域并没有对应的这些状态字段

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