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Intel手册-Chapter1

发表于 2015 年 10 月 28 日

1.3         NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for
hexadecimal and binary numbers. A review of this notation makes the manual easier to read.
关于数据结构格式,本手册使用了特殊的标记方法,关于指令被符号替代,十六进制和二进制,回顾符号将使手册更容易的去读
1.3.1     Bit and Byte Order    二进制位和字节的规则
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses
increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to
two raised to the power of the bit position. IA-32 processors are “little endian” machines; this means the bytes of
a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.
下面插入了关于数据结构的图片,低地址朝向底部,高地址朝向顶部,二进制位被从右往左编号,The numerical value of a set bit is equal to
two raised to the power of the bit position这句话不会翻译,IA-32是小端类型,也就是说,一个word类型的数据,是从最低有效位(LSB )开始编号的(LSB-MSB是小端排序,MSB-LSB是大端排序),Figure 1-1的图片,说明了这些约定:


1.3.2     Reserved Bits and Software Compatibility    保留位和软件兼容性
In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as
reserved, it is essential for compatibility with future processors that software treat these bits as having a future,
though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable.
Software should follow these guidelines in dealing with reserved bits:
在一些寄存器和内存的描述中,一些位被标记为保留位,当这些位被标记为保留位时,关于以后的处理器和软件对待这些位,它拥有最基本的兼容性,尽管不知道对于以后的影响,保留的这些位的行为也应该不仅仅被视为未定义,但是不可预测的,软件应该在处理有关保留位的行为中,遵循下面的准则
•   Do not depend on the states of any reserved bits when testing the values of registers which contain such bits.
Mask out the reserved bits before testing.
当测试的寄存器的值中包含保留位时,应该不要信赖这些位的任何状态,应该在测试之前,屏蔽它们
• Do not depend on the states of any reserved bits when storing to memory or to a register.
当向内存或者寄存器存入值时,应该不要信赖任何保留位的状态
• Do not depend on the ability to retain information written into any reserved bits.
不要相信把有用的信息,写入任何保留位的能力
• When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or
reload them with values previously read from the same register.
当加载一个寄存器的时候,文档中若指定了这个值,要总是加载这些保留位,如果文档中没有说明,要重新加载从相同的寄存器读取的上次的值
NOTE
Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon
the values of reserved register bits will make software dependent upon the unspecified manner in
which the processor handles these bits. Programs that depend upon reserved values risk incompatibility
with future processors.
避免任何软件信赖 IA-32位寄存器上的保留位,处理器处理这些位时,信赖寄存器保留位的值,将会使软件发生不可预测的行为,程序信赖值的保留位,对于将来的处理器,将会发生不兼容的危险

1.3.3    Instruction Operands    指令操作数
When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset,
an instruction has the following format:
当指令被符号代替的时候,IA-32汇编语言的子集将被使用,在这个子集中,一个指令应该遵循如下格式
label: mnemonic argument1, argument2, argument3
where:
• A label is an identifier which is followed by a colon.
lable是一个跟随者“:”的标识符
• A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
助记符是一类与指令码有相同功能的保留名字
• The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands,
depending on the opcode. When present, they take the form of either literals or identifiers for data items.
Operand identifiers are either reserved names of registers or are assumed to be assigned to data items
declared in another part of the program (which may not be shown in the example).
When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left
operand is the destination.
操作数参数1,参数2,参数3是可选项,它们可以不存在,也可以有三个参数,至于有几个参数,取决于操作码,当这些参数存在的时候,它们的形式可以是寄存器的保留名,也可以是“数据标识符”       (szText  db   '1234',0        这里szText就是数据标识符 ),被宣布在程序的另一部分,当两个操作数都存在算术或者逻辑指令的时候,右边的操作数是源操作数,左边的操作数是目的操作数
For example:
LOADREG: MOV EAX, SUBTOTAL
In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,
and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
在这个例子中,LOADREG是一个操作码的助记符标识符,EAX是目的操作数,SUBTOTAL 是源操作数,一些汇编语言会把源操作数和目的操作数交换位置
1.3.4 Hexadecimal and Binary Numbers              十六进制和二进制数
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for
example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, and F.
十六进制数是用一个以“H”结尾的十六进制字符串所表示,一个十六进制数是一个从0-F的字符
Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for
example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might
arise.
二进制数是用一个1s和0s的字符串来表示的,有时以字符“B”结尾,指定字符B,仅仅被用作可能引起与数字混淆的位置
1.3.5        Segmented Addressing       分段寻址
The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.
Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes in memory. The
range of memory that can be addressed is called an address space.
处理器使用的是字节寻址,这也就是说,内存的组织和访问是以一系列的字节开始的,无论是访问一个字节或者更多字节,字节寻址总是用来确定内存中一个字节或者更多字节的位置,内存中能被寻址的范围叫做地址空间
The processor also supports segmented addressing. This is a form of addressing where a program may have many
independent address spaces, called segments. For example, a program can keep its code (instructions) and stack
in separate segments. Code addresses would always refer to the code space, and stack addresses would always
refer to the stack space. The following notation is used to specify a byte address within a segment:
处理器也支持分段寻址,一个程序也许有许多独立的地址空间,这种地址被叫做段,比如,一个程序能使它的代码和栈在不同的段,代码寻址将一直引用代码空间,栈寻址将一直引用栈空间,下面的标识被用作指定了一个段内的地址
Segment-register:Byte-address
段寄存器:字节-地址
For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS
例如,下面的段地址标识了由DS指向的段内的地址FF79H
register:
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the
code segment and the EIP register contains the address of the instruction.
下面的段地址标识了代码段内的指令地址,CS寄存器指向了代码段 ,EIP寄存器包含了指令地址
CS:EIP
1.3.6     Exceptions    异常
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions.
Some types of exceptions may provide error codes. An error code reports additional information about the
error. An example of the notation used to show an exception and error code is shown below:
当指令发生错误的时候,异常是一个典型的事件。例如,一个试图除零的操作会产生一个异常,然而,一些异常,例如断点异常,是发生在其他环境下,一些类型的异常也许提供错误码,错误码会报道关于错误更多的额外信息,用于显示异常和错误码的标识的例子如下
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is
reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate
code. In this case, the error code is zero, as shown below for a general-protection exception:
这个例子引用了一个,在错误代码命名为错误的类型环境下的页面异常被报道,在其他环境下,异常产生错误码的错误码也许并不完全正确,
这种情况下,错误码是零,下面的例子,显示的就是一个通用保护异常
#GP(0)
1.3.7 A New Syntax for CPUID, CR, and MSR Values    关于CPUID, CR, MSR的新的语法
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
用CPUID获得flags的标志状态,系统信息,通过检查控制寄存器位和读取MSR寄存器,我们正用新的语法来展现这些信息, See Figure 1-2

1.4 RELATED LITERATURE    相关文献
Literature related to Intel 64 and IA-32 processors is listed on-line at:  关于32位和64位处理器的文献,被列举在了下面一行
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature available
is listed by Intel processor and then by the following literature types: applications notes, data sheets, manuals,
papers, and specification updates.
See also:
• The data sheet for a particular Intel 64 or IA-32 processor
• The specification update for a particular Intel 64 or IA-32 processor
• Intel® C++ Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
• Intel® Fortran Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
• Intel® VTune™ Performance Analyzer documentation and online help:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
• Intel® 64 and IA-32 Architectures Software Developer’s Manual (in three or five volumes):
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
• Intel® 64 and IA-32 Architectures Optimization Reference Manual:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimizationmanual.
html
• Intel 64 Architecture x2APIC Specification:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-architecture-x2apic-specification.
html
• Intel® Trusted Execution Technology Measured Launched Environment Programming Guide:
http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
• Developing Multi-threaded Applications: A Platform Consistent Approach:
http://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdf
• Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor:
http://software.intel.com/en-us/articles/ap949-using-spin-loops-on-intel-pentiumr-4-processor-and-intelxeonr-
processor/
• Performance Monitoring Unit Sharing Guide
http://software.intel.com/file/30388
More relevant links are:
• Software network link:
https://software.intel.com/en-us
• Developer centers:
http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html
• Processor support general link:
http://www.intel.com/support/processors/
• Software products and packages:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
• Intel® Hyper-Threading Technology (Intel® HT Technology):
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm

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